1. Field of the Invention
The present invention relates to a method of and an apparatus for placing and routing elements of a semiconductor integrated circuit, and more particularly, to a method of and an apparatus for placing and routing elements of a semiconductor integrated circuit with the use of a computer.
2. Description of the Related Art
A computer aided design (CAD) system is used to design a semiconductor integrated circuit (IC). This system requires a method of and an apparatus for speedily and easily placing and routing elements of the IC while reducing skew (skew time), wiring overhead, and propagation delay times in the IC.
The prior art adopted for CAD systems first prepares a net list involving various cells, and then routes the cells. This technique is insufficient in various points. Concretely, in the prior art, a time dependent layout technique for placing and routing elements of a semiconductor IC is provided.
For example, in this prior art time dependent layout technique, a very long time is required to complete the placing and routing of a semiconductor IC. Note that the prior art suppresses skew by adjusting load capacitance and by employing balanced wiring, snaking wiring, and star wiring. In addition, the prior art must secure a margin of space to suppress skew. This reduces an available area for logic circuits.
Further, the prior art must artificially induce delays at a high speed terminal (fast terminal) relative to a terminal (slow terminal) that receives a signal behind the high speed terminal, to suppress skew. This increases the overall time delay in producing the IC. An IC production operation usually involves temporal fluctuations due to variations in temperature, processes, and source voltages. These fluctuations affect time delay in the IC. The prior art, therefore, must consider a margin for absorbing such fluctuations.